The present invention relates to a reset pulse signal generating circuit, more specifically to a technique that prevents a write error caused by a sudden change of the power supply voltage or during the power being turned on.
When there occurs a sudden drop of the power supply voltage during a normal operating state or during an input of the power supply, the nonvolatile memory such as a flash memory can cause an unexpected delete of data, namely a write error. Especially, in a single supply voltage type flash memory, for example, all of the high voltages necessary for rewrite of data are generated in the chip of itself. Therefore, during an input of the power supply, or during an instant stop of the power supply, if the control circuit misidentifies it as a data rewrite command, the write error will surely be created.
In order to avoid this write error, a power supply level monitor circuit is effective.
The power supply level monitor circuit, including a direct current path, has a circuit that cuts off the direct current path during standby by means of a power-down signal added thereon In most cases.
However, during receiving the power-down signal, a cut-off of the direct current path will make the power supply level monitor circuit inoperative, whereby the rewrite control circuit cannot be initialized. Therefore, a complete prevention of the write error cannot be achieved, which is a problem to be solved.
With the foregoing in view, it is therefore an object of the present invention to provide a reset pulse generating circuit for preventing the write error of the semiconductor memory circuit.
A reset pulse signal generating circuit of the present invention comprises an output node and an output circuit connected to the output node and outputting the reset pulse signal and a first MOS transistor having a first conductivity type connected between a first power supply source and the output node. The first MOS transistor is turned on in response to the write signal. The reset pulse generating circuit further comprises a second MOS transistor having a second conductivity type connected between the output node and a second power supply source and a power supply transition detector connected to the first and second power supply sources and the second MOS transistor. The power supply transition detector outputs a transfer signal having a level which is determined by a level of the power supply sources when the write signal is in an inactive state. Further, the power supply transition detector outputs the transfer signal having a predetermined level when the write signal is In the active state.
Typical ones of various inventions of the present application have been shown in brief. However, the various inventions of the present application and specific configurations of these inventions will be understood from the following description.